Method and apparatus for eliminating contention with dual bus masters
US6438686B1 · kind B1 · utility
5Cited by
11References
23Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Apr 20, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for eliminating contention with dual masters. One method disclosed disables a default bus master, and tests for a second bus master. If the second bus master fails to respond, the default bus master is enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.