High speed parallel bit error rate tester
US6438717B1 · kind B1 · utility
151Cited by
2References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 9, 1999 |
| Grant date | Aug 20, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high speed link between chips and comprising a multiplicity of synchronous serial data channels includes an onboard detector for detecting an error rate for each channel. The transmitter and the receiver chips are configured in response to the detector to select the channel having the lowest error rate as the control channel and optionally to render at least the channel with the highest error rate inactive.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.