Integrated circuit including passivated copper interconnection lines and associated manufacturing methods
US6440852B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jul 30, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/958
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a substrate, and at least one copper interconnection layer adjacent the substrate. The interconnection layer further comprises copper lines, each comprising at least an upper surface portion including at least one copper fluoride compound. The copper fluoride compound preferably comprises at least one of cuprous fluoride and cupric fluoride. The compounds of copper and fluoride are relatively stable and provide a reliable and long term passivation for the underlying copper. In accordance with one particularly advantageous embodiment of the invention, the dielectric layer may comprise a fluorosilicate glass (FSG) layer. Accordingly, during formation of the FSG layer, the upper surface of the copper reacts with the fluorine to form the copper fluoride compound which then acts as the passivation layer for the underlying copper. In other embodiments, the dielectric layer may comprise an oxide or air, for example. In yet other embodiments, the copper line may include prefluorinated portions so as to avoid fluorine depletion of adjacent FSG layer portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.