Device with integrated bipolar and MOSFET transistors in an emitter switching configuration
US6441446B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/121
Abstract
The device is constituted by an N+ substrate, by an N− layer on the substrate, by a metal contact for a collector, by a buried P− base region, by a P+ base contact and insulation region within which an insulated N region is defined, by a metal contact on the base contact region for a base, by an N+ emitter region buried in the insulated region and forming a pn junction with the buried base region, by a P+ body region in the insulated region, by an N+ source region in the P+ region, by a metal contact for a source, and by a gate electrode. In order to achieve a low resistance Ron, the P+ body region extends as far as the buried N+ emitter region and an additional N+ region is provided within the body region and constitutes a drain region, defining, with the source region, the channel of a lateral MOSFET transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.