Method and apparatus for determining phase locked loop jitter
US6441602B1 · kind B1 · utility
10Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 26, 2000 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Oct 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/205
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An exemplary embodiment of the invention is a method for evaluating jitter of a phase locked loop circuit generating a phase locked loop output signal. The method includes generating a test initiate signal and generating a trigger signal in response to the test initiate signal. The trigger signal is synchronized with the phase locked loop output signal. A disturbance signal is generated to induce jitter in the phase locked loop output signal. The jitter in the phase locked loop output signal is then evaluated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.