Multiplexers for efficient PLD logic blocks
US6441642B1 · kind B1 · utility
17Cited by
8References
22Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Feb 20, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1736
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic section of a programmable logic device comprising a first circuit and a second circuit. The first circuit may be configured to generate a first output in response to a first input, a second input and a third input. The second circuit may be configured to generate a second output and a third output in response to a fourth input and a fifth input. The second output may be coupled to the second input and the first output may be coupled to the fifth input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.