PLL cycle slip compensation
US6441691B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Mar 16, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/199
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Phase-reset circuits provide first and second frequency-divided input signals to a phase/frequency detector (PFD) used in a phase-locked loop (PLL). The phase-reset circuits receive first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD generates control signals based on the phase difference between the frequency-divided input signals. Normally, the phase-reset circuits frequency divide the first and second input signals using divisors N and M, respectively. If other circuitry detects that the PFD has missed a clock cycle in the first or second clock-divided input signals, the corresponding phase-reset circuit alters its divider so that the next clock edge on the corresponding input signal clocks through to the PFD. This causes the PFD to quickly set its affected control signal to what it would have been had the clock cycle not been missed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.