PLL frequency synthesizer
US6441692B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 17, 1998 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Sep 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention provides a high-speed PLL frequency synthesizer in which the frequency of a reference signal can be made larger than a frequency interval of an external output with a simple configuration. An n-th harmonic of an output of a voltage-controlled oscillator is caused to pass through a band pass filter. The frequency of an output of the band pass filter is divided by M in a variable frequency divider. The phase of an output of the variable frequency divider is compared with that of the reference signal in a phase comparator. An output of the phase comparator is smoothed by a loop filter. The output of the voltage-controlled oscillator is controlled by an output of the loop filter. The fundamental wave of the output of the voltage-controlled oscillator is caused to pass through another band pass filter, and then output to the outside. At this time, the frequency of the reference signal is n times a frequency interval of the fundamental wave of the output of the voltage-controlled oscillator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.