Memory module for preventing skew between bus lines
US6442057B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jun 21, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10159
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module for preventing skew between bus lines is provided. The memory module includes a printed circuit board, memory chips, module tabs and bus lines. The memory chips are disposed on the printed circuit board, and the module tabs are disposed at one edge of the printed circuit board. The bus lines are connected to the module tabs, respectively, and are connected to the memory chips. Each of the bus lines is formed a closed circuit loop. Each of the bus lines is connected to the memory chips through a circuitous or roundabout path which includes first and second paths of, in general, different lengths. The first and second paths of the roundabout path branch from each other at a position on the closed circuit loop. Since each bus line on the memory module forms a closed loop, skew does not occur between control signals or output data, which are transmitted through the bus line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.