High performance multi-bank compact synchronous DRAM architecture
US6442098B1 · kind B1 · utility
83Cited by
4References
11Claims
0Family size
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Key dates
| Filing date | Feb 6, 2001 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Feb 6, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the virtual memory banks has coupled to it an associated segmented sense amp which responds to an appropriate bank select signal by sensing data stored in a selected memory bank segment. The segmented sense amp uses a segmented bit line to reduce bit sense latency without decreasing bit density or increasing chip size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.