System and method for data alignment in a communication system
US6442178B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1998 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Oct 1, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A parallel-to-serial-to-parallel circuit are disclosed, the circuit interfacing with a data bus, preferably with a processor for byte alignment and other operations. The parallel-to-serial-to-parallel circuit includes an input bit shift register having a predetermined number of register positions and an output bit shift register with the same number of register positions. The output of the input bit shift register is fed into the output bit shift register through a multiplexer. The input bit shift register may receive a bit write from a bit bus, a partial parallel write from a data bus with corresponding data validity data received on a shadow bus, and full parallel write from the data bus. The output bit shift register may transmit a bit read to the bit bus or a full parallel read to the data bus. Data received is shifted to the output bit shift register and compiled into full parallel data or read out as single bits. Offset bits may be introduced in the data stream for data alignment. The present invention also provides a further advantage of including the ability to perform various bit stuffing and bit scrambling operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.