Multi-phase-locked loop for data recovery
US6442225B1 · kind B1 · utility
35Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 14, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jun 14, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0891
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a multi-phase-locked loop without dead zone, which can reduce clock jitter and provide larger tolerance for data random jitter. It generates and output multiple sets of control signals (upk/dnk) via a multi-phase voltage controlled oscillator which generates a plurality of multi-phase clock signals for detecting the transition edge of data signal. Therefore, the phase error &thgr;e and the voltage Vd of the multi-phase-locked loop can be adjusted to be nearly linear according to the control signals. A multi-phase-locked loop without dead zone thus can be provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.