Digital isolation system with low power mode

US6442271B1 · kind B1 · utility

Assignee

• Silicon Laboratories Inc. · US

Inventors

• George Tyson Tuttle · Austin, US
• Jerrell P. Hein · Driftwood, US
• Timothy J. Dupuis · Austin, US
• Jeffrey W. Scott · Austin, US
• Navdeep S. Sooch · Emmaus, US
• David R. Welland · Austin, US

Key dates

• Filing date: Mar 4, 1998
• Grant date: Aug 27, 2002
• Expiry date: Mar 4, 2018

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02D30/70
• WIPO field: Telecommunications
• WIPO sector: Electrical engineering

Abstract

A method and apparatus are provided for maintaining communication across an isolation barrier even if the external circuitry to which it is connected enters a low-power mode. In normal operation the isolation barrier local clock is synchronized with a clock signal provided by the external circuitry. If the external circuitry enters a low-power mode, its clock signal often slows or stops. In that case, the local clock in the isolation barrier switches to a free-running mode, wherein a VCO voltage input is provided by a bias voltage generator instead of by a PLL circuit. The VCO thus continues to provide a local clock signal in order to allow communication of information across the isolation barrier even if the external circuitry is not active. This enables the isolation barrier to receive and process an external signal, such as a ring signal, in low-power mode. Means are provided for causing the external circuitry to “wake up” in the event that a ring or other signal is detected by the isolation system, at which time the system resumes normal operation.