Handling multiple delayed write transactions simultaneously through a bridge
US6442641B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Jun 8, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embodiment of the invention is directed at a method of processing multiple delayed write transactions, such as PCI transactions, by a bridge. The method involves receiving a number of requests for delayed write transactions on an initiating side of the bridge, and storing received transaction information for each of the requests in a separate one of a number of storage elements. An element containing newly received transaction information is marked valid if no received transaction information in other elements matches the newly received transaction information. Then, a delayed write transaction corresponding to the valid element is mastered on a target side of the bridge. If the corresponding delayed write transaction is completed on the target side, then the valid element is marked as complete. Thereafter, a new request received on the initiating side is signaled a successful termination if received transaction information for the new request matches that stored in the valid and complete element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.