Load based cache control for satellite based CPUs
US6442652B1 · kind B1 · utility
26Cited by
3References
28Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 7, 1999 |
| Grant date | Aug 27, 2002 |
| Priority date | — |
| Expiry date | Sep 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The effect of Single Event Upsets (SEUs) occurring in cache memory (103) utilized in satellites is reduced. The idle time of a processor (102), utilizing cache memory (103), is monitored. If processor (102) idle time reaches a predetermined minimum (205), cache memory (103) is engage. When processor (102) idle time subsequently reaches a predetermined maximum threshold (203), cache memory (103) is disabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.