Semiconductor device having a memory cell with a plurality of active elements and at least one passive element
US6445026B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 26, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jul 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device capable of reducing a cell area without affecting the accuracy, capable of reducing the number of interconnection layers, and capable of realizing a hybrid circuit of a memory cell and peripheral circuit easily and at a low cost, including a bit line, a word line, control gate line, a capacitor with a first electrode connected to the word line, a read transistor comprising an NMOS connected between the bit line and a predetermined potential point and with a gate electrode connected to a second electrode of a capacitor, and a write transistor comprising an NMOS connected between the bit line and the second electrode of the capacitor and with a gate electrode connected to the control gate line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.