Semiconductor memory cell array with reduced parasitic capacitance between word lines and bit lines
US6445041B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/12
Abstract
Provided is a semiconductor memory device in which SRAM has a construction such that an nMOS transistor formation region and a pMOS transistor formation region are disposed in a direction along which a bit line extends, thereby reducing delay in the bit line caused by wiring parasitic capacity. A main word line has a shape such that the main word line is disposed every two memory cell rows avoiding a bit line contact and part of the main word line extends to the row adjacent to the two rows. Accordingly, the main word line can be easily formed in the layer below the bit lines. In the bit lines, wiring parasitic capacity between the main word line and the bit line is reduced and therefore delay in the bit line is eliminated. As a result, time delay in memory operation is reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.