Bipolar junction transistor incorporating integral field plate

US6445058B1 · kind B1 · utility

Assignee

• Legerity, Inc. · US

Inventors

• Frank L. Thiel · Sachse, US
• William E. Moore · Macedon, US
• Philip Shiota · Saratoga, US

Key dates

• Filing date: May 17, 2000
• Grant date: Sep 3, 2002
• Expiry date: May 17, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/133

Abstract

A semiconductor process is disclosed which forms a field plate structure that integrally contacts an emitter region of a bipolar junction transistor by construction, without intervening interconnect layers or contacts. In one embodiment, a single-layer polysilicon electrode forms a field plate electrode which integrally interconnects to a traditional diffused emitter region formed before the polysilicon layer is deposited. This allows for deeper emitter regions required by the deep base regions needed for high-voltage bipolar devices. Moreover, the polysilicon layer, including the polysilicon electrode forming the field plate electrode, may be used as a local interconnect layer.