Circuit topology for better supply immunity in a cascaded Gm/Gm amplifier
US6445250B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 12, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | May 12, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F3/45183
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
There is disclosed an amplifier comprising: 1) a plurality of cascaded NMOS differential amplifier stages, wherein a first one of the plurality of cascaded NMOS differential amplifier stages is coupled to at least one input signal; 2) a PMOS differential amplifier stage having a first input coupled to a first NMOS differential output of a last one of the plurality of cascaded NMOS differential amplifier stages and a second input coupled to a second NMOS differential output of the last cascaded NMOS differential amplifier stage, wherein the PMOS differential amplifier comprises a first diode-connected PMOS load transistor having a gate and a drain connected to ground and a second diode-connected PMOS load transistor having a gate and a drain connected to ground; and 3) an output differential amplifier stage comprising: a) load transistors comprising a third PMOS transistor having a gate and a drain connected together and a source connected to a power supply rail and a fourth PMOS transistor having a gate coupled to the third PMOS transistor gate and a source connected to the power supply rail; and b) a differential transistors pair comprising a first NMOS transistor having a gate co…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.