High speed precision analog to digital convertor
US6445326B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 22, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jun 22, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/504
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog to digital convertor includes a pulse width modulated circuit (PWM) responsive to an analog parameter of an analog signal. The PWM circuit generates a pulse having a duty cycle proportional to the analog parameter. A counter generates a plurality of counterpulses during the pulse duty cycle and a sub-cycle pulse generator generates a series of subcycle pulses during each of the counterpulses. A latch circuit latches the state of the subcycle pulse generator at a predetermined time relative to the termination of the PWM pulse and a logic circuit counts the number of counterpulses which are generated during the PWM pulse. A most significant bit number is represented by the number of counter-pulses and a least significant bit number is determined by the state of the subcycle pulses in the latch. These two numbers added together provide a digital number representative of the analog parameter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.