Semiconductor device having stacked semiconductor elements
US6445594B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jul 20, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A lower semiconductor element is mounted facing down on an insulating circuit board, and an upper semiconductor element is stacked facing up on the lower semiconductor element. Openings are provided in the insulating circuit board at a location facing the element electrodes of the lower semiconductor element, and the element electrodes of the lower semiconductor element are connected to the board electrodes on the lower surface of the insulating circuit board through the openings. Also, the element electrodes of the upper semiconductor element are connected to the board electrodes on the upper surface of the insulating circuit board. Thus, a high-density semiconductor device is provided by stacking a plurality of semiconductor elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.