Dynamic range reduction circuitry for a digital communications receiver
US6445732B1 · kind B1 · utility
33Cited by
20References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 23, 1998 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Sep 23, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B17/318
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A method and apparatus which reduces the computational complexity of a receiver subject to power swings in excess of the power swings inherent in wireless communication from normal fading. To accomplish this, attenuation or some other form of signal modification occurs prior to the digital circuitry to reduce the required resolution of the analog to digital converter and other receiver components. A power signal estimator in conjunction with an attenuation control module may control the level of attenuation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.