Partially-synchronous high-speed counter circuits
US6445760B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jul 14, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/588
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Partially-synchronous and non-integer integrated circuit counters for dividing a high-speed reference clock signal with a selectable divisor have been provided. The circuits use a high-speed synchronous counter that cycles between the use of a selectable and a fixed divisor, to give the counter circuit a selectable overall division ratio. The partially-synchronous counter circuit uses asynchronous dividers to complete the division process and to minimize power consumption. A non-integer counter circuit is provided that includes a edge select mechanism to reduce power consumption in the division process. Examples are presented with specific number of stages, and corresponding divisors and divisor ranges. Method for implementing the above-mentioned partially-synchronous and non-integer counter circuits have also been provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.