Processor emulation virtual memory address translation
US6446034B1 · kind B1 · utility
45Cited by
11References
21Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 16, 1998 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2009/45583
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When emulating a Target architecture on a Host system having a different architecture, virtual to real address translation is typically expensive in terms of computer cycles. The cost can be significantly reduced by utilizing direct page table pointers to short-circuit the address translation. In a system additionally supporting segments framing portions of virtual memory, the direct page table pointers are associated with segment registers and point to the page table entry corresponding to the first location in a segment. Direct page table pointers are invalidated when underlying virtual memory management tables are modified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.