Double precision floating point multiplier having a 32-bit booth-encoded array multiplier
US6446104B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Sep 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/49994
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A double-precision multiplier for use in the floating point pipeline of a processor has an array multiplier and a carry-save partial-product accumulator. Double precision multiplication is accomplished by generating a plurality of partial products and summing these in the carry-save partial-product accumulator. The partial-product accumulator has a carry-save adder, a sum register, a carry-out counter and an extender. The carry-out counter receives a carry outputs of the carry-save adder and array multiplier, and the extender is coupled to extend the sum register dependent upon the contents of the carry-out counter. The extension occurs during addition of the most significant partial product to the sum of less significant partial products.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.