Computer memory compression abort and bypass mechanism when cache write back buffer is full
US6446145B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jan 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a processing system having a main memory wherein information is stored in a compressed format for the purpose of gaining additional storage through compression efficiencies, a method and apparatus for enabling termination of a pending compression operation for the purpose of writing the data directly to the main memory, bypassing the compressor hardware during stall conditions. Memory space (compressibility) is sacrificed for higher system performance during these temporary write back stall events. A background memory scrub later detects and recovers the “lost” compressibility by recycling the uncompressed data back through the compressor during idle periods.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.