Self-modifying synchronization memory address space and protocol for communication between multiple busmasters of a computer system
US6446149B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1998 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Mar 3, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system provides a self-modifying synchronization memory address space and protocol for communication between multiple busmasters. In one computer system embodiment, the self-modifying synchronization memory address space is provided in a memory controller embedded in a peripheral device of the computer system such as a bridge that provides central, high speed access by a busmaster to the memory controller without accessing a host bus. The synchronization memory address space includes a set of semaphore memory cells mapped to shared critical resources in the computer system. The semaphore memory cell allows for exclusive access by a busmaster to a shared critical resource by switching itself from an idle state to a busy state responsive to a first read operation by a busmaster. In the busy state of the semaphore memory cell, a busy state is communicated to other busmasters which attempt to read the semaphore memory cell. Ownership of the semaphore memory cell is thus achieved using a single operation by a busmaster. The properties of the self-modifying synchronization memory address space and the semaphore memory cell thus eliminate the need for assertion of a bus locking…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.