System having a configurable cache/SRAM memory

US6446181B1 · kind B1 · utility

Assignees

• Intel Corporation · US
• Analog Devices, Inc. · US

Inventors

• Hebbalalu S. Ramagopal · Austin, US
• David B. Witt · Austin, US
• Michael S. Allen · Union Gap, US
• Moinul Syed · Austin, US
• Ravi Kolagotla · Austin, US
• Lawrence A. Booth, Jr. · Phoenix, US
• William C. Anderson · Austin, US

Key dates

• Filing date: Mar 31, 2000
• Grant date: Sep 3, 2002
• Expiry date: Mar 31, 2020

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/16
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus having a core processor and a memory system is disclosed. The core processor includes at least one data port. The memory system is connected in such a way as to provide substantially simultaneous data accesses through the data port. The memory system can be made user configurable to provide appropriate memory model.