Method and apparatus for single cycle processing of data associated with separate accumulators in a dual multiply-accumulate architecture
US6446193B1 · kind B1 · utility
24Cited by
13References
24Claims
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Key dates
| Filing date | Sep 8, 1997 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Sep 8, 2017 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3885
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for reducing instruction cycles in a digital signal processor wherein the processor includes a multiplier unit, an adder, a memory, and at least one pair of first and second accumulators. The accumulators include respective guard, high and low parts. The method and apparatus enable vectoring the respective first and second high parts from the accumulators to define a single vectored register responsive to a single instruction cycle and processing the data in the vectored register.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.