Debug mechanism for data processing systems
US6446221B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | May 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/3648
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for processing data is provided, said apparatus comprising: a main processor 4 responsive to main processor instructions within a stream of instructions input to said main processor 4 to perform main processor operations; a coprocessor 6 coupled to said main processor 4 via a coprocessor interface CP and responsive to coprocessor instructions MCR, MRC within said stream of instructions to perform coprocessor operations; wherein said coprocessor 6 is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor. Using a debug mechanism in the form of a debug coprocessor reduces the impact of the debug mechanism upon normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.