Semiconductor memory device
US6446227B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 23, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Dec 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The semiconductor memory device of the present invention is characterized in the provision of: data amps provided to each output terminal for amplifying the voltage of data read out from a memory cell, outputting the result as a first output data, and outputting a second output data which is generated from this first output data; a data compressing circuit for compressing the first output data from each the output terminal, and performing testing to determine whether or not this first output data read out from the memory cell is normal based on the compressed results; a plurality of first lines for outputting each the first output data to the data compressing circuit from the data amps; and a second line for connecting and outputting the second output data from the data amps to the data compressing circuit using a wired OR.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.