Cumulative error detecting code
US6446235B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An error detection technique uses a cumulative error detecting code (such as a cumulative CRC checksum or the like). At the source node (transmitter side) an error detecting code of a previous cell is stored. The next cell to be transmitted is received and the error detecting code of the previous cell is appended to the next cell. A next error detecting code is calculated as a function of at least a portion of the next cell to be transmitted and the previous error detecting code appended thereto. The previous error detecting code appended to the next cell is replaced with the next error detecting code, and the next cell including the next error detecting code appended thereto is transmitted. In this manner, the cumulative error detecting code is calculated over the current cell and a previous error detecting code. Thus, the cumulative error detecting code can be used to detect bit errors in each individual cell as well as to detect one or more missing or dropped cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.