Method and apparatus for optimizing electronic design
US6446239B1 · kind B1 · utility
54Cited by
21References
40Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 7, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Jan 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is disclosed for compacting an initial electronic layout of cells within an initial layout boundary. The system includes forming paths extending from a bottom edge of the layout to a top edge. The paths intersect cells of the initial layout. The system determines which of the paths are critical paths. Critical cuts are then determined. A critical cut is a cut that severs critical paths. A set of cells associated with a critical cut are removed from the layout and replaced in order to reduce the initial layout boundary.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.