Automated method for testing cache
US6446241B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Nov 15, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0831
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method generates a list of allowed states in a cache design by applying each input transaction sequentially to all found legal cache states. If application of an input transaction to a current search cache results in a new cache state, then this new cache state is added to the list of legal cache states and to a list of search cache states. This is repeated for all input transactions and all such found legal cache states. At the same time a sequence of input transactions reaching each new cache state is formed. This new sequence is the sequence of input transactions for the prior cache state and the current input transaction. The method generates a series of test sequences from the list of allowed states and their corresponding sequence of input transactions which are applied to the control logic cache design and to a reference memory. If the response of the control logic cache design fails to match the response of the reference memory, then a design fault is detected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.