Method for functional verification of VLSI circuit designs utilizing reusable functional blocks or intellectual property cores
US6446243B1 · kind B1 · utility
29Cited by
25References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 23, 1999 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Apr 23, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Computer-assisted apparatus/method functionally verifies circuit design through automatic generation of verification rules from reusable functional block or IP core using logic simulator and input stimuli. Rule base captures set of design states or scenarios.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.