Method and apparatus for socket-based design with reusable-IP
US6446251B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Mar 31, 2000 |
| Grant date | Sep 3, 2002 |
| Priority date | — |
| Expiry date | Mar 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for socket-based design with reusable intellectual property (IP) includes a chip integration system (CIS) that provides designers with a convenient method to create and describe a system on a chip (SOC) design independent of design flow. A Chip Integration Description Language (CIDL) is also disclosed that provides a mechanism for defining interfaces between IP cores in a way that isolates a system designer from much of the connection information previously required is also disclosed. Using CIDL, a system designer is able to rapidly connect multiple blocks of intellectual property (IP) based upon the functionality of the blocks rather than traditional hardware-specific connection methods. The details pertaining to specific connections that may be needed are encapsulated within a CIDL-based file that is typically written by the IP core designer. The actual connection of signals between blocks of IP, however, is performed by a CIDL compiler that uses the CIDL file(s) as input.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.