Method for fabricating self-aligned field emitter tips
US6448100B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jun 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J9/025
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
An efficient and economical method for fabricating field emitter tips within a layered substrate. The layered substrate is patterned using standard photolithographic techniques and etched to form a rectangular or cylindrical column on top of the substrate composed of conductive and non-conductive layers. The layered substrate is then exposed to an anisotropic etching medium which removes the column to produce a well through the conductive and non-conductive layers and which produces a conical or pyramid-shaped field emitter tip within the silicon substrate directly below the well. Finally, a pull-back etch is used to remove dielectric material from the walls of the well. In an optional step, a thin metal coating may be sputtered onto the surface of the silicon-based field emitter tip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.