Wiring method for producing a vertical, integrated circuit structure and vertical, integrated circuit structure
US6448174B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Oct 5, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The invention relates to a wiring method for vertical system integration. According to the method described in the invention, the individual component layers in different substrates are first processed independently of each other in accordance with the state of the art (DE 44 33 846 A1) and then assembled. First, via holes are opened up on the front side of the top substrate which preferably pass through all the component layers present. The top substrate is then thinned from the rear side as far as the via holes, after which a fully processed bottom substrate is joined to the top substrate. Next, the via holes are extended (so-called interchip via holes) as far as a metallized level of the bottom substrate and the contact between the top and bottom substrates is established (wiring). According to the present invention the wiring is carried out in a way which allows for a maximum density of the vertical contacts between the metallization of the top substrate and that of the bottom substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.