Adaptive biasing of RF power transistors
US6448616B1 · kind B1 · utility
5Cited by
3References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 14, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Aug 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/432
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A power transistor according to one embodiment of the invention includes a plurality of transistor elements located on a single semiconductor die, each transistor element comprising one or more transistors coupled to a common gate terminal for the respective transistor element. A resistor network couples the transistor element gate terminals between a bias voltage and a reference ground, with resistors in the network sized such that such that a first transistor element is biased in a first, e.g., class A, operating condition, and a second transistor element is biased in a second, e.g., class AB operating condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.