Selective netlist to test fine pitch multi-chip semiconductor
US6448796B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2000 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Nov 8, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system for testing every one of the signal inputs and outputs (I/O) of a fine pitch multi-chip semiconductor module utilizing a selective netlist, through the intermediary of presently available test equipment. More particularly, the system facilitates the testing of fine pitch multi-chip modules utilizing 1.0 mm ceramic column grid array (CCGA) technology in order to facilitate the use of increased system interconnect capabilities. Additionally, there is provided a method of employing a selective netlist in order to test fine pitch multi-chip semiconductor modules; especially such as, but not limited to 1.0 mm pitch ceramic column grid array (CCGA) modules by employing commercially available test equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.