Low hold time statisized dynamic flip-flop
US6448829B1 · kind B1 · utility
13Cited by
9References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 7, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jun 7, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/35625
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A low hold time flip-flop that has a dynamic input stage and a static output stage is provided. The flip-flop uses a feedback stage to maintain a value on a dynamic node during an evaluation phase of the flip-flop so that an input to the flip-flop only has to be held for a relatively short period of time after the start of the evaluation phase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.