True single-phase flip-flop
US6448831B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jun 12, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/44
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Undersired glitches in output signals from TSPC-1 flip-flop circuits having an output stage comprising an node and a second node are removed by precharging the second node (prior to a clock transition) to a value desired at the output node during a period following the clock transition, and connecting the output node to the second node upon such clock transition. Corrective circuitry illustratively comprising two NMOS transistors added to the output stage and receiving an input reflecting the desired future output is active during a portion of the operating cycle when the output stage exhibits a high impedance tristate condition.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.