Method and apparatus for convolution encoding and viterbi decoding of data that utilize a configurable processor to configure a plurality of re-configurable processing elements
US6448910B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 26, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Mar 26, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/6563
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for convolution encoding and Viterbi decoding utilizes a flexible, digital signal processing architecture that comprises a core processor and a plurality of re-configurable processing elements arranged in a two-dimensional array. The core processor is operable to configure the re-configurable processing elements to perform data encoding and data decoding functions. A received data input is encoded by configuring one of the re-configurable processing elements to emulate a convolution encoding algorithm and applying the received data input to the convolution encoding algorithm. A received encoded data input is decoded by configuring the plurality of re-configurable processing elements to emulate a Viterbi decoding algorithm wherein the plurality of re-configurable processing elements is configured to accommodate every data state of the convolution encoding algorithm. The core processor initializes the re-configurable processing elements by assigning register values to registers that define parameters such as constraint length and code rate for the convolution encoding algorithm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.