1-T memory structure capable of performing hidden refresh and an operating method applied thereto
US6449205B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 15, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jun 15, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This invention relates to a 1-T memory structure capable of performing hidden refresh and an operating method applied to the structure, which uses a data latch and an electrically parallel path to effectively solve the lost data problem in the art from the collision of access actions and refresh actions. The structure includes: a plurality of memory arrays for storing data signal; a plurality of sense amplifiers for amplifying the data signal of the respective memory array and temporarily storing the amplified data signal; a selector for selecting the amplified data signal through a bus based on a cycle-indicative signal; and a shared data latch for receiving and storing the data signal from the selector.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.