Semiconductor memory device comprising more than two internal banks of different sizes
US6449209B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 19, 2001 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a plurality of internal banks of different sizes. The internal banks are suitable for and correspond to the memory needs of a plurality of master devices. Master devices are assigned banks having sizes matched to the needs of the master devices so that inclusion of multiple buffers in a bank can be avoided. A master device that requires a small buffer is assigned a memory bank having a small size, and an external master that requires a large amount of memory is assigned a large bank. Reduction of the average number of master devices sharing each bank improves performance by reducing the number of page misses caused when different master interleave accesses of different pages in the same bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.