Time division multiplexed synchronous state machine having state memory
US6449292B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1997 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Nov 9, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/0623
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
An implementation of a synchronous state machine, responsive to a time division multiplexed external input signal having plural time slots in a repetitive structure, has all of its flip-flop outputs hooked up to a state memory so that the state produced by each time slot is stored until that time slot is again repeated at the external input, at which point the stored state is recalled from memory for being input along with the incoming time slot data; in this way the hardware is shared between time slots. A substitution element is disclosed having a flip-flop with its output routed to memory and for providing a memory output as its output. A design methodology is taught whereby a state memory and a substitution element is substituted for each flip-flop in a synchronous state machine implemented for one time slot of a repeating pattern of time slots.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.