Multiple function processing core for communication signals
US6449630B1 · kind B1 · utility
6Cited by
10References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 7, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Apr 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/5443
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus for processing digital signals includes a multiplier having a first input and a second input and an output producing a product. An adder is connected to receive the product from the multiplier as a first input to produce a sum. A first register is connected to receive and store the sum and to provide a second input to the adder in response to a clock signal. A second register is connected to receive and store the output of the first register in response to an inverse of the clock signal to enable the addition of two products in a single clock cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.