Method and apparatus for busing data elements
US6449671B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1999 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Jun 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for busing data elements within a computing system includes processing that begins by providing, on a shared bus, a first control signal relating to a first transaction during a first bus cycle. The processing continues by providing a second control signal relating to a second transaction and a first address signal relating to the first transaction during a second bus cycle. The processing continues by providing a third control signal relating to a third transaction and a second address signal relating to a second transaction during a third bus cycle. The processing then continues by providing a first status relating to the first transaction and a third addressing signal relating to the third transaction during a fourth bus cycle. The processing then continues by providing a second status relating to the second transaction during a fifth bus cycle. The processing then continues by providing first data relating to the first transaction when the first status is a hit and providing third status relating to the third transaction during a sixth bus cycle.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.