Field programmable processor using dedicated arithmetic fixed function processing elements
US6449708B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 1998 |
| Grant date | Sep 10, 2002 |
| Priority date | — |
| Expiry date | Dec 4, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A field programmable processor includes a regular array of processing elements, each of which is adapted to perform a fixed arithmetic function on packets of data. The processing elements are interconnected by an array of signal conductors extending adjacent the processing elements. Switching means are provided for selectively connecting the processing elements to the adjacent signal conductors so as to interconnect the processing elements. Program data representing desired processing element interconnections is stored, the switches are controlled in accordance with the stored program data to achieve the desired processing element interconnections. The packets of data are transmitted between the interconnected processing elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.