Column grid array for flip-chip devices
US6449840B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1998 |
| Grant date | Sep 17, 2002 |
| Priority date | — |
| Expiry date | Sep 29, 2018 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49165
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for providing C4-type bumps which are higher than conventional C4 bumps. A dielectric substrate is copper cladded on both sides. At each prospective bump location, a via is laser ablated through the cladded substrate. A copper core is deposited within the vias to thereby connect the two claddings. A photoresist is applied to both claddings, a photomask having a predetermined exposure pattern is placed over the claddings, the photoresist is exposed to ultraviolet (UV) light to thereby polymerize in the exposed areas thereof, and the resulting photoresist image is developed by use of a developer solution to wash away of the unpolymerized areas of the photoresist. Now, the photoresist image provides a retainer wall spaced from, and circumferentially around, the vias. Next, a lead-tin solder alloy is electroplated, such as by a lead-tin fluoroborate bath, at the vias into the volumes defined by the retainer wall at each end of the vias. Now, the photoresist is stripped, such as by an alkali stripper, from the cladding, leaving behind a pair of solder deposits at each via. Next, the copper cladding is etched away using an ammonia based etchant, wherein the solder deposits are l…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.